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http://www.interfacebus.com/Design_Connector_PCI_Express.html
PCI Express
PCI Express is the new serial bus addition to the PCI series of specifications. This is a serial bus which uses two low-voltage differential LVDS pairs, at 2.5Gb/s in each direction [one transmit, and one receive pair]. PCI Express uses 8B/10B encoding [each 8 bit byte is translated into a 10 bit character in order to equalize the numbers of 1's and 0's sent, and the encoded signal contains an embedded clock]. PCI Express supports 1x [2.5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs].
The PCI Express bus started showing up on Mother Boards in 2004 as an addition (using a new connector) to PCI, than will coexist and out-pace parallel PCI at the rate PCI took over from the ISA bus. One common PCIe implementation seems to have two 1x PCI Express slots and one 16x PCIe slot [used to replace the AGP slot], then some number of standard parallel (classic) PCI slots [3 to 4="4"].
PCI-X
The Peripheral Component Interface [PCI-X] addendum is an enhancement to the current 64 bit 66MHz PCI bus specification. The minimum clock speed for PCI-X is 66MHz [PCI-X 66]. Additional bus speeds include: PCI-X 133, PCI-X 266 and PCI-X 533 providing up to 4.3GBps [PCI-X 1066 in the works]. PCI-X is backwards compatible with PCI; of course none of the enhancements would be available and the best speed would revert to 66MHz. PCI-X provides for the same card form factor, pin-outs, connector, bus widths, and protocols. Many of the changes relate to bus operation, wait states and protocol enhancements, which is not covered here. PCI-X still supports either 32 bit or 64 bit bus widths.
