http://arstechnica.com/wankerdesk/3q02/powerpc.html
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* L1 data cache: 32 KB
* L1 instruction cache: 64 KB
* L2 cache: 512K
Registers:
* 32 64-bit general purpose registers
* 32 64-bit floating-point registers
* 32 128-bit vector registers
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One of the most important and least-discussed features of the PowerPC 970 is its 900MHz DDR frontside bus. This bus physically runs at 450MHz, but it´s double-pumped.
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raw peak data bandwidth is supposed to be about 6.4 GB of that 7.2 GB/s.
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The estimated SPEC INT and SPEC FP numbers (937 and 1051) would allow the 970 to clearly dominate the desktop scene were it released tomorrow, but by the time we see this chip in a shipping system the performance landscape will look significantly different in both the 32-bit (P4 at 4GHz+ with SMT) and 64-bit (AMD´s Hammer) desktop markets.
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